In this project you will design the multi-cycle datapath for the modified MIPS-Lite (MML) ISA from homework #2 (and summarized below). You will model and verify your design using the Verilog Hardware Description Language (HDL).
** Note that with permission, you can implement a different version of the MML ISA if you can justify why your solution to homework #2 is better than the proposed solution.
The project involves seven major steps (note, steps 3 – 5 can be done concurrently):
Step 1. Design instruction formats for the MML ISA (Done in homework #2 and summarized below).
Step 2. Design the multi-cycle datapath for the MML ISA and the Main Controller’s Finite State Machine
Step 3. Write Verilog HDL models of the multi-cycle datapath components (as described below). Individually test each component (module).
Step 4. Design and model the main controller and ALU controller and test.
Step 5. Write a MML ISA machine code benchmark to fully test the integrated datapath design.
Step 6. Integrate the components to build the complete multi-cycle datapath. Test your design using the benchmark designed in step 5.
Step 7. Write your project report describing all aspects of the design from steps 1 through 6. Your report should be technical and comprehensive.
The MML ISA is a load-store architecture with the following specifications,
• 8 registers, where register 0 is always zero.
• A 16-bit word.
• Byte addressable memory.
• A one-word instruction with the 4 following instruction formats:
R-format [opcode = 5 bits][rs = 3 bits][rt = 3 bits][rd = 3 bits][func = 2 bits]
I-format [opcode = 5 bits][rs = 3 bits][rt = 3 bits][immediate = 5 bits]
IL-format [opcode = 5bits][rs = 3 bits][immediate = 8 bits]
J-format [opcode = 5 bits][address = 11 bits]
• Six addressing modes:
o Immediate addressing:
addiu $1,$2, imm # $1 = $2 + 5-bit immediate deskPD