Computer Architecture (Logisim)
Model the designed 32×32-bit register file as one single module in logisim and test the register file for correct operation by writing to and reading from different register combinations.
Register File 32 5 5 5 BusA RA RB 32 BusB Clock BusW 32 RegWrite
-BusA and BusB: 32-bit data output busses for reading 2 registers. During read operation, the register file behaves as a combinational block and once the RA or RB have valid data, the content of the read register will appear on BusA or BusB after a certain access time.
-RegWrite: control signal to enable/disable register writing operation. When RegWrite is 1, register write is enabled; otherwise, is disabled.
-BusW: 32-bit data input bus for writing a register when RegWrite is 1
-RA: 5-bits selection lines to select the register to be read on BusA.
-RB: 5-bits selection lines to select the register to be read on BusB
-RW: 5-bits selection lines to select the register to be to be written with BusW.
Show transcribed image text